GS81302S09GE sram equivalent, 144mb sigmasio ddr -ii burst of 2 sram.
* Simultaneous Read and Write SigmaSIO™ Interface
* JEDEC-standard pinout and package
* Dual Double Data Rate interface
* Byte Write controls sampled at d.
where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular .
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input —
R/W
Read/Write Contol Pin
Input Write Active Low; Read Active High
NW0
–NW1
Synchronous Nybble Writes
Input
Active Low x08 Version
BW0
.
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